AT91SAM9XE512-QU【PDF 9/159 页】MCU ARM9 512K FLASH 208-PQFP

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PIC16F62X

DS40300C-page 104

Preliminary

2003 Microchip Technology Inc.

FIGURE 14-16:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 14-10: SUMMARY OF WATCHDOG TIMER REGISTERS

14.9

Power-Down Mode (SLEEP)

The Power-down mode is entered by executing a

SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the STATUS register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before SLEEP was executed (driving high, low, or hi-

impedance).

For lowest current consumption in this mode, all I/O

pins should be either at V

DD, or VSS, with no external

circuitry drawing current from the I/O pin and the com-

parators, and V

REF should be disabled. I/O pins that

are hi-impedance inputs should be pulled high or low

externally to avoid switching currents caused by float-

ing inputs. The T0CKI input should also be at V

DD or

SS for lowest current consumption. The contribution

from on-chip pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (V

IHMC).

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR Reset

Value on all

other

RESETS

2007h

Config.

bits

LVP

BODEN

MCLRE

FOSC2

PWRTE

WDTE

FOSC1

FOSC0

uuuu uuuu

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

Legend:

_ = Unimplemented location, read as “0”, + = Reserved for future use

Note

1: Shaded cells are not used by the Watchdog Timer.

(Figure 6-1)

Note

1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

From TMR0 Clock Source

Watchdog

Timer

WDT

Enable Bit

8 to 1 MUX

PS<2:0>

To TMR0

(Figure 6-1)

PSA

WDT

Timeout

PSA

MUX

WDT POSTSCALER/

TMR0 PRESCALER

Note:

It should be noted that a RESET generated

by a WDT timeout does not drive MCLR

pin low.

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